Automated Stem Angle Determination for Temporal Plant Phenotyping Analysis

Image-based plant phenotyping analysis refers to the monitoring and quantification of phenotyping traits by analyzing images of the plants captured by different types of cameras at regular intervals in a controlled environment. Extracting meaningful phenotypes for temporal phenotyping analysis by considering individual parts of a plant, e.g., leaves and stem, using computer-vision based techniques remains a critical bottleneck due to constantly in- creasing complexity in plant architecture with variations in self-occlusions and phyllotaxy. The paper introduces an algorithm to compute the stem angle, a potential measure for plants’ susceptibility to lodging, i.e., the bending of stem of the plant. Annual yield losses due to stem lodging in the U.S. range between 5 and 25%. In addition to outright yield losses, grain quality may also decline as a result of stem lodging. The algorithm to compute stem angle involves the identification of leaf-tips and leaf-junctions based on a graph theoretic approach. The efficacy of the proposed method is demonstrated based on experimental analysis on a publicly available dataset called Panicoid Phenomap-1. A time-series clustering analysis is also performed on the values of stem angles for a significant time interval during vegetative stage life cycle of the maize plants. This analysis effectively summarizes the temporal patterns of the stem angles into three main groups, which provides further insight into genotype specific behavior of the plants. A comparison of genotypic purity using time series analysis establishes that the temporal variation of the stem angles is likely to be regulated by genetic variation under similar environmental conditions

A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture

The highest levels of security can be achieved through the use of more than one type of cryptographic algorithm for each security function. In this paper, the REDEFINE polymorphic architecture is presented as an architecture framework that can optimally support a varied set of crypto algorithms without losing high performance. The presented solution is capable of accelerating the advanced encryption standard (AES) and elliptic curve cryptography (ECC) cryptographic protocols, while still supporting different flavors of these algorithms as well as different underlying finite field sizes. The compelling feature of this cryptosystem is the ability to provide acceleration support for new field sizes as well as new (possibly proprietary) cryptographic algorithms decided upon after the cryptosystem is deployed.Defence Science Journal, 2012, 62(1), pp.25-31, DOI:http://dx.doi.org/10.14429/dsj.62.143

Automated Stem Angle Determination for Temporal Plant Phenotyping Analysis

Image-based plant phenotyping analysis refers to the monitoring and quantification of phenotyping traits by analyzing images of the plants captured by different types of cameras at regular intervals in a controlled environment. Extracting meaningful phenotypes for temporal phenotyping analysis by considering individual parts of a plant, e.g., leaves and stem, using computer-vision based techniques remains a critical bottleneck due to constantly in- creasing complexity in plant architecture with variations in self-occlusions and phyllotaxy. The paper introduces an algorithm to compute the stem angle, a potential measure for plants’ susceptibility to lodging, i.e., the bending of stem of the plant. Annual yield losses due to stem lodging in the U.S. range between 5 and 25%. In addition to outright yield losses, grain quality may also decline as a result of stem lodging. The algorithm to compute stem angle involves the identification of leaf-tips and leaf-junctions based on a graph theoretic approach. The efficacy of the proposed method is demonstrated based on experimental analysis on a publicly available dataset called Panicoid Phenomap-1. A time-series clustering analysis is also performed on the values of stem angles for a significant time interval during vegetative stage life cycle of the maize plants. This analysis effectively summarizes the temporal patterns of the stem angles into three main groups, which provides further insight into genotype specific behavior of the plants. A comparison of genotypic purity using time series analysis establishes that the temporal variation of the stem angles is likely to be regulated by genetic variation under similar environmental conditions

Effect Of Trapped Charge In Algan/Gan And Algan/Ingan/Gan Heterostructure By Temperature Dependent Threshold Voltage Analysis

The effect of trap energy states in AlGaN/InGaN/GaN heterostructure is investigated by temperature dependent threshold voltage measurement from 298 K to 373 K. It is found that the threshold voltage of AlGaN/InGaN/GaN structure decreases from - 6.52 V to - 6.90 V with temperature increase from 298 K to 348 K. But for the temperature higher than 348 K, the threshold voltage starts to increase and reaches to - 6.75 V at 373 K. However, the threshold voltage for AlGaN/GaN structure decreases consistently from −5.32 V to −6.4 V for entire range of temperature. The decrease of threshold voltage is attributed to the surface donor trap charges for both the heterostructures. Furthermore, the acceptor trap charges might have contributed for temperature above 348 K, and hence the increase of threshold voltage is observed in AlGaN/InGaN/GaN heterostructure. Higher crystal defects, resulted from lower growth temperature, might be responsible for the formation of these acceptor trap levels in InGaN layer

Off-State Leakage And Current Collapse In Algan/Gan Hemts: A Virtual Gate Induced By Dislocations

The existence of a correlation between current collapse and off-state reverse-bias leakage current in heteroepitaxially grown AlGaN/GaN high-electron-mobility transistors is investigated from the perspective of conductive threading dislocations. Collapsed current response (recoverable) to synchronized gate-drain voltage pulses is found to be governed by the epilayer\u27s dislocation density, and also by the off-state quiescent bias scheme. Furthermore, magnitudes of reverse-gate leakages apart from being dislocation density dependent are found to have distinctive temperature-bias characteristics. Based on the trapping spatiality along with field and temperature dependence of the respective leakage currents; an emission mechanism is postulated involving donor-like surface states and dislocation induced deep levels. It is inferred that dislocations can indeed be responsible for the current collapse that has been long assumed to be caused by the surface states

Energy Aware Synthesis of Application Kernels expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

With transistor energy efficiency not scaling at the same rate as transistor density and frequency, CMOS technology has hit a utilization wall, whereby large portions of the chip remain underclocked. To improve performance, while keeping power dissipation at a realistic level, future computing devices will consist of heterogeneous application specific accelerators. The accelerators have to be synthesised from high level specifications and will be specialized for related classes of application kernels. In this paper we explore synthesizing application kernels expressed as functions, on a coarse grained composable reconfigurable array (CGCRA). The CGCRA consists of a set of reconfigurable datapaths called HyperCells, each of which can either compute an individual kernel, or can be composed together to compute a larger kernel. The proposed synthesis approach takes kernels expressed in a functional language, applies a sequence of well known program transformations, explores trade-offs between throughput and energy, and realizes the kernels on the CGCRA

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

Transistor supply voltages no longer scales at the same rate as transistor density and frequency of operation. This has led to the Dark Silicon problem, wherein only a fraction of transistors can operate at maximum frequency and nominal voltage, in order to ensure that the chip functions within the power and thermal budgets. Heterogeneous computing systems which consist of General Purpose Processors (GPPs), Graphic Processing Units (GPUs) and application specific accelerators can provide improved performance while keeping power dissipation at a realistic level. For the accelerators to be effective, they have to be specialized for related classes of application kernels and have to be synthesized from high level specifications. Coarse Grained Reconfigurable has been proposed as accelerators for a variety of application kernels. For CGRAs to be used as accelerators in the Dark Silicon era, a synthesis framework which focuses on optimizing energy efficiency, while achieving the target performance is essential. However, existing compilation techniques for CGRAs focuses on optimizing only for performance, and any reduction in energy is just a side-effect. In this paper we explore synthesizing application kernels expressed as functions, on a coarse grained composable reconfigurable array (CGCRA). The proposed reconfigurable array comprises HyperCells, which are reconfigurable macro-cells that facilitate modeling power and performance in terms of easily measurable parameters. The proposed synthesis approach takes kernels expressed in a functional language, applies a sequence of well known program transformations, explores trade-offs between throughput and energy using the power and performance models, and realizes the kernels on the CGCRA. This approach when used to map a set of signal processing and linear algebra kernels achieves resource utilization varying from 50% to 80%

Compiling HPC Kernels for the REDEFINE CGRA

In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communicate through messages. REDEFINE offers the ability to exploit high degree of coarse-grain and pipeline parallelism. The CEs in REDEFINE are enhanced with reconfigurable macro data-paths called HyperCells that enable exploitation of fine-grain and pipeline parallelism at the level of basic instructions in static dataflow order. Application kernels that exhibit regularity in computations and memory accesses such as affine loop nests benefit from the architecture of HyperCell 1], 2]. The proposed compilation flow aims at exposing high degree of parallelism in loop nests in HPC application kernels using polyhedral analysis and generates meta-data to effectively utilize the computational resources in HyperCells. Memory is explicitly managed through compiler's assistance. We address the compilation challenges such as partitioning with load balancing, mapping and scheduling computations and management of operand data while targeting multiple HyperCells in the REDEFINE architecture. The proposed solution scales well meeting the performance objectives of HPC computing

RHyMe: REDEFINE HyperCell Multicore for Accelerating HPC Kernels

In this paper, we present an architecture named REDEFINE HyperCell Multicore (RHyMe) designed to efficiently realize HPC application kernels, such as loops. RHyMe relies on the compiler to generate the meta-data for its functioning. Most of the orchestration activity for executing kernels is governed by compiler generated meta-data made use of at runtime. In RHyMe, macro operations can be realized as a hardware overlay of MIMO operations on hardware structures called HyperCells. While a HyperCell enables exploiting fine-grain instruction level and pipeline parallelism, coarse-grain parallelism is exploited among multiple HyperCells. Regularity exhibited by computations such as loops results in efficient usage of simple compute hardware such as HyperCells as well as memory structures that can be managed explicitly